[libmaple] SDIO

[michael_l]

I think Steve is using a modified (better: more actual) branch of the SDfat library, you could install this one:
https://github.com/stevstrong/SdFat
So here you can see the DMA changes:
https://github.com/stevstrong/SdFat/blo ... iSTM32.cpp
Beware if your SDFat library is global that it might not working with other cores (I'm always try to include them not global but in /hardware// -> libraries for each core)
Steves branch must be used with caution (In his F1 maple mini is broken, caused by a new ADC structure).

Thanks ! I tried that and it works. I was under impression that SdFat under Steve's F4 repo would be working.

[stevestrong]

As Matthias said, use the SdFat lib and SPI lib from my repo, i updated them lately exactly because of this issue.
Which was caused because i added versions of SPI dma function transfer().

[flyboy74]

Victor,
1. As far as I know:
- the SDIO 1 bit mode rd/wr performance is below the SPI performance.
- the number of pins needed for SDIO 1 bit mode is equal to number of pins needed by SPI.
- SDIO is available only for HIGH_LINE devices, where the number of pins is large enough.
Considering these, the SDIO 1 bit mode it only makes really sense if there is no free GPIO left and no free SPI port left on the chip, which I cannot really imagine.
However, you could implement it for the F1 line if you want, for the F4 family, where there are a lot of GPIOs available, I wouldn't bother.

2. I agree, the clock should be best calculated from the current PLL and clock settings.
- But the time I developed that, I considered that for F4 I will anyway use only the 168MHz. Anyway, feel free to add the feature you want.

Ok as always I am a noob but I will still post what my understating is and the experience that I have and anyone can correct me if I am wrong as it is how I learn.

I have used SD in SPI, 1_line and 4_line a reasonable bit in Micro-Python and a bit on STM32F4 with Cube MX, HAL and FATFS.

SPI has the advantage that if your going to need SPI for other things then you will need the MOSI, MISO and CLK lines anyway so it will just use an extra CS pin. But in my experience it is limited to using the SD card at a max of 25Mhz as the SPI is on the APB1 clock and can't run in High Speed mode of 50Mhz.

SD 1_line uses I less line that SPI as it doesn't have a CS pin but can be used in high speed mode of 50Mhz as SDIO is on the APB2 so if you don't need the SPi bus for anything else it saves I line and is possible to have twice the transfer rate as SPI.

SD 4_Line uses 2 more lines than SPI but is 4 bits wide and can also be used in high speed mode so can get transfers at 8 times the speed as SPI

A quick google I found this

sd.JPG (54.87 KiB) Viewed 274 times

[stevestrong]

SPI_1 runs with 42mhz and is usable.

Sdio cannot run with 42mhz due to a hw issue, chech the errata sheet. At least in 4bit mode, i dont know in 1 bit mode.

[flyboy74]

SPI_1 runs with 42mhz and is usable.

Sdio cannot run with 42mhz due to a hw issue, chech the errata sheet. At least in 4bit mode, i dont know in 1 bit mode.

Thanks Stevestrong.

I did just google the doc and have a bit of a read but didn't really understand what it was saying so I don't understand the problem.

The doc seems to contradict the reference manual too which quotes this

SDIO_CK is the clock to the card: one bit is transferred on both command and data lines
with each clock cycle.
The SDIO uses two clock signals:
• SDIO adapter clock SDIOCLK up to 50 MHz (48 MHz when in use with USB)
• APB2 bus clock (PCLK2)
PCLK2 and SDIO_CK clock frequencies must respect the following condition:
Frequenc(PCLK2) ≥ 3 ⁄ 8 × Frequency(SDIO_CK)

[stevestrong]

Which doc?
Where is the contradiction?

I did just google the doc and have a bit of a read but didn't really understand what it was saying so I don't understand the problem.

Well, in this case I would not dig deeper.

[flyboy74]

Which doc?
Where is the contradiction?

I did just google the doc and have a bit of a read but didn't really understand what it was saying so I don't understand the problem.

Well, in this case I would not dig deeper.

Then I will never understand. I like learning new things.

Is this the problem you refer too??

SDIO clock divider BYPASS
mode may not work properly

If I am understanding this properly this means that you can't bypass the divider so that means if you don't bypass(i.e BYPASS bit is equal to "0") and use the min value for the divider then max speed of SDIO will be 42MHz

Is this the HW problem you talk about???

[flyboy74]

Will it work if you setup SDI clock control register (SDIO_CLKCR) like this??
Bit 10 BYPASS = 0
Bits 7:0 CLKDIV = 0

where SDIO_CK frequency = SDIOCLK / [CLKDIV + 2].
This gives 82MHz / [0 +2] = 42MHz

With clocks setup like this??

clocks.JPG (49.74 KiB) Viewed 251 times

[stevestrong]

I am referring to:

2.11.6 No underrun detection with wrong data transmission
Description
In case there is an ongoing data transfer from the SDIO host to the SD card and the hardware flow control is disabled (bit 14 of the SDIO_CLKCR is not set), if an underrun condition occurs, the controller may transmit a corrupted data block (with wrong data word) without detecting the underrun condition when the clock frequencies have the following relationship:
[3 x period(PCLK2) + 3 x period(SDIOCLK)] >= (32 / (BusWidth)) x period(SDIO_CK)
Workaround
Avoid the above-mentioned clock frequency relationship, by:
• Incrementing the APB frequency
• or decreasing the transfer bandwidth
• or reducing SDIO_CK frequency

As workaround, there is only the last option feasible, if we want to keep USB (48Mhz), and no overclocking. The next available frequency lower than 48MHz is the half of it, 24MHz.

[flyboy74]

OK thanks for the explanation. I am now a little smarter than 1 hr ago.

I do see 2 options
1. SDIO 1_line running at 42Mhz
2. SDIO 4_line running at 24MHz

If both of these options work then SDIOI 1_line will be same speed at SPI and SDIO 4_line will be double the speed of SPI